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The Search for the Perfect Microarchitecture
Understanding Area, Power, and Performance using TinyXPU
Jul 12
•
Bharath Suresh
and
Avik De
12
5
The Art of Architectural Analysis: Utilization, Throughput, Latency
Putting TinyXPU Under the Microscope
Mar 30
•
Bharath Suresh
and
Avik De
16
3
Mapping Algorithms to Custom Silicon - Part 2
Running matrix multiplication on a TPU-style architecture
Mar 15
•
Bharath Suresh
and
Avik De
13
2
2
Mapping algorithms to custom silicon - Part 1
An introduction to the messy middle between software and microarchitecture
Feb 9
•
Bharath Suresh
and
Avik De
33
4
Understanding on-chip networks
How different components of your chip talk to each other
Aug 25, 2025
•
Bharath Suresh
36
2
5
Confessions of a static timing analysis tool
All about STA, from the horse's mouth
Jul 21, 2025
•
Bharath Suresh
18
3
3
Power essentials for a chip architect
All you need to know about power as a chip designer
Jun 7, 2025
•
Bharath Suresh
35
3
4
Caches Deep Dive - Part 2: Optimization Techniques
In part 1 of the Caches Deep Dive series, I covered some basic concepts in designing a cache.
Feb 8, 2025
•
Bharath Suresh
2
1
Caches Deep Dive - Part 1: The Basics
Introduction to caches
Jan 25, 2025
•
Bharath Suresh
4
2
What does CPU bitness mean?
When you look at CPU specs, one of the first things you would see is what's called "bitness" - 8 bit, 16 bit, 32 bit or 64 bit CPUs.
Dec 21, 2024
•
Bharath Suresh
6
2
The ISA Debate
If you have even remotely followed the processor industry, you would have heard about "ARM vs x86".
Oct 27, 2024
•
Bharath Suresh
8
In-Order Instruction Pipelining in Processors
Before going into this topic, I want to define the way I am using some terms here:
Sep 29, 2024
•
Bharath Suresh
7
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