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Life of an Inference Call
A complete walkthrough of LLM inference running on your computer
Sep 14
•
Bharath Suresh
17
5
4
The Search for the Perfect Microarchitecture
Analyzing Area, Power, and Performance using TinyXPU
Jul 12
•
Bharath Suresh
and
Avik De
29
1
8
The Art of Architectural Analysis: Utilization, Throughput, Latency
Putting TinyXPU Under the Microscope
Mar 30
•
Bharath Suresh
and
Avik De
18
3
Mapping Algorithms to Custom Silicon - Part 2
Running matrix multiplication on a TPU-style architecture
Mar 15
•
Bharath Suresh
and
Avik De
14
2
2
Mapping algorithms to custom silicon - Part 1
An introduction to the messy middle between software and microarchitecture
Feb 9
•
Bharath Suresh
and
Avik De
37
5
Understanding on-chip networks
How different components of your chip talk to each other
Aug 25, 2025
•
Bharath Suresh
37
2
5
Confessions of a static timing analysis tool
All about STA, from the horse's mouth
Jul 21, 2025
•
Bharath Suresh
19
3
3
Power essentials for a chip architect
All you need to know about power as a chip designer
Jun 7, 2025
•
Bharath Suresh
36
3
4
Caches Deep Dive - Part 2: Optimization Techniques
How to build a faster memory architecture
Feb 8, 2025
•
Bharath Suresh
3
1
Caches Deep Dive - Part 1: The Basics
Introduction to caches
Jan 25, 2025
•
Bharath Suresh
5
2
What does CPU bitness mean?
The number of CPUs that makes them sell
Dec 21, 2024
•
Bharath Suresh
7
2
The ISA Debate
Frequently asked questions about Instruction Set Architectures
Oct 27, 2024
•
Bharath Suresh
9
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