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The Art of Architectural Analysis: Utilization, Throughput, Latency
Putting TinyXPU Under the Microscope
Mar 30
•
Bharath Suresh
and
Avik De
13
2
Mapping Algorithms to Custom Silicon - Part 2
Running matrix multiplication on a TPU-style architecture
Mar 15
•
Bharath Suresh
and
Avik De
13
2
2
ENIAC and the Workload Problem - Part 1
Why studying ENIAC Matters - Especially now.
Mar 9
•
Bharath Suresh
11
4
5
February 2026
Mapping algorithms to custom silicon - Part 1
An introduction to the messy middle between software and microarchitecture
Feb 9
•
Bharath Suresh
and
Avik De
30
4
January 2026
The Accidental Comeback of Verilog
How Generative AI is ending the HDL vs HLS debate
Jan 17
•
Bharath Suresh
17
4
3
The Computer Architecture Calendar
An annual ritual of hype, validation, and existential dread
Jan 4
•
Bharath Suresh
20
2
3
December 2025
The Alphabet Soup of Processors
Not sure which will end first: Moore’s Law, or alphabets used to describe processors?
Dec 15, 2025
•
Bharath Suresh
14
9
5
What should I write if AI can write everything?
What next for Chip Insights
Dec 7, 2025
•
Bharath Suresh
17
6
1
September 2025
Letter to the subscribers - Year 1
Thoughts on a year writing Chip Insights
Sep 20, 2025
•
Bharath Suresh
15
6
2
August 2025
Understanding on-chip networks
How different components of your chip talk to each other
Aug 25, 2025
•
Bharath Suresh
35
5
The bad old days of debugging
The computer engineering version of “kids, back in our time…”
Aug 18, 2025
•
Bharath Suresh
12
4
4
The psychology of a technical interview
The non-technical aspects that no one talks about
Aug 4, 2025
•
Bharath Suresh
11
1
2
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