Very well written! I agree that a lot of literature talks about - the CPU, memory design but the interconnect is just as important. The flight analogies made this easy to understand.
Can't help but see a lot of parallels between internet networks and Network on Chips - packet size, congestion control, path lengths etc . After all they're both networks.
Excited to dive deeper into NoCs.
As I understood - the term on chips means all these nodes exist on a single chip and are connected internally using a network,
I had a questions
1. Two terms were used on-chip networks and Network on Chips. If i understand correctly, they mean the same and are interchangeable?
2. When designing a component of chip then, I must pre decide how my network looks like, as the design of the router of each chip is dependent on the type of network?
Hey, thanks for the comment, glad you liked the post. Some very good points, here’s what I think:
1 - In this post, they are definitely interchangeable. I think that’s the case in general too.
On-Chip Networks is a colloquial way of saying “Here’s something that connects different blocks on your chip”. A lot of old literature seems to use this term. But this paper introduced the terminology of Network on Chip - https://ieeexplore.ieee.org/document/976921
They seem to define NoC as “Layered Micronetworks” - so you could argue each Micronetwork can be considered an “On-Chip Network.”
In general, I’ve seen the NoC terminology used together with System-On-Chips (SoCs.) On Chip Networks could be for any type of chip.
But this is a good question, I’d love to hear back if you actually find a better answer.
2 - Ideally, yes, because you can design a very optimized router if you already know what the network looks like. But in practice, I think it’s more co-design between the components (like CPU, GPU, NPU) and the network connecting them. So, we use standard routers than can scale across different networks (usually by changing the buffering needed, or the arbitration protocols.)
Very well written! I agree that a lot of literature talks about - the CPU, memory design but the interconnect is just as important. The flight analogies made this easy to understand.
Can't help but see a lot of parallels between internet networks and Network on Chips - packet size, congestion control, path lengths etc . After all they're both networks.
Excited to dive deeper into NoCs.
As I understood - the term on chips means all these nodes exist on a single chip and are connected internally using a network,
I had a questions
1. Two terms were used on-chip networks and Network on Chips. If i understand correctly, they mean the same and are interchangeable?
2. When designing a component of chip then, I must pre decide how my network looks like, as the design of the router of each chip is dependent on the type of network?
Hey, thanks for the comment, glad you liked the post. Some very good points, here’s what I think:
1 - In this post, they are definitely interchangeable. I think that’s the case in general too.
On-Chip Networks is a colloquial way of saying “Here’s something that connects different blocks on your chip”. A lot of old literature seems to use this term. But this paper introduced the terminology of Network on Chip - https://ieeexplore.ieee.org/document/976921
They seem to define NoC as “Layered Micronetworks” - so you could argue each Micronetwork can be considered an “On-Chip Network.”
In general, I’ve seen the NoC terminology used together with System-On-Chips (SoCs.) On Chip Networks could be for any type of chip.
But this is a good question, I’d love to hear back if you actually find a better answer.
2 - Ideally, yes, because you can design a very optimized router if you already know what the network looks like. But in practice, I think it’s more co-design between the components (like CPU, GPU, NPU) and the network connecting them. So, we use standard routers than can scale across different networks (usually by changing the buffering needed, or the arbitration protocols.)
I’m pretty new to this topic too, I recommend you check out this slide-deck which talks about the internals of a router - https://www.ecb.torontomu.ca/~courses/coe838/lectures/NoC-Router-MicroArchitecture.pdf