Great post, and I totally agree that GenAI seems a great tool to fill this "interface gap", especially coupled with taking advantage of the verifiability of Verilog at the tail end.
Is the high-level intent specified in the form of text?
Also, are there any open-source or easily accessible libraries that allow one to try something like this out? If companies keep the models proprietary (understandable), maybe there is some room for an open-source effort to generate and train something like this.
Hey Avik, some interesting questions here. I don't think we have all the answers yet, but it's a space I'm keenly following.
High level intent coming from natural language seems like the intention - which people are calling "Natural Language Synthesis (NLS)" in recent research papers. This is the way forward in theory, but it's going to be a challenge to integrate this with existing design - so I personally think Verilog still has a very long rope.
There are open source model trained/fine-tuned specifically for Verilog - Verigen is one I've followed for a while. There's also open source EDA tools (I have talked about them here if you are interested: https://chipinsights.net/p/eda-deep-dive-part-2-open-source)
I think stiching this all together is where the challenge and opportunity lies.
Haha, Verilog ftw!
Ok perfect, I never learned HLS and I guess I never will. Long love Verilog!
VHDL is easier for LLM than Verilog
I'm curious, can you explain why you think that's the case?
Too many bad software-like Verilog code out there, LLM learnt from bad examples.
VHDL code in the wild is a lot cleaner.
People hated VHDL because it is hard to write, but LLM doesn't care those tedious syntax.
It's a fair concern. Maybe someone with better experience training LLMs can give an answer: Which one is better?
1. A lot of average examples
2. A few high-quality examples
Great post, and I totally agree that GenAI seems a great tool to fill this "interface gap", especially coupled with taking advantage of the verifiability of Verilog at the tail end.
Is the high-level intent specified in the form of text?
Also, are there any open-source or easily accessible libraries that allow one to try something like this out? If companies keep the models proprietary (understandable), maybe there is some room for an open-source effort to generate and train something like this.
Hey Avik, some interesting questions here. I don't think we have all the answers yet, but it's a space I'm keenly following.
High level intent coming from natural language seems like the intention - which people are calling "Natural Language Synthesis (NLS)" in recent research papers. This is the way forward in theory, but it's going to be a challenge to integrate this with existing design - so I personally think Verilog still has a very long rope.
There are open source model trained/fine-tuned specifically for Verilog - Verigen is one I've followed for a while. There's also open source EDA tools (I have talked about them here if you are interested: https://chipinsights.net/p/eda-deep-dive-part-2-open-source)
I think stiching this all together is where the challenge and opportunity lies.